Full Reverse Engineering of the TI-84 Plus Operating System
Key takeaways
- CPU: Zilog Z80 (16-bit address bus, 64 Ki B logical space) with hardware flash/RAM paging.
- Confidence is flagged: [confirmed] = verified in disassembly/decompiler; [standard] = matches documented TI-83+/84+ architecture and is consistent with the disassembly; [hypothesis] = inferred, not yet verified.
- The TI-84+ is a Z80 machine that can only see 64 Ki B at once, but has 1 MiB of flash and 128 KiB of RAM.
Target: ti84plus.rom (1 Mi B flash dump). OS self-identifies as 2.55MP. CPU: Zilog Z80 (16-bit address bus, 64 Ki B logical space) with hardware flash/RAM paging. Ghidra project: ti84.gpr (rebuild: tools/build.sh).
Confidence is flagged: [confirmed] = verified in disassembly/decompiler; [standard] = matches documented TI-83+/84+ architecture and is consistent with the disassembly; [hypothesis] = inferred, not yet verified.
The TI-84+ is a Z80 machine that can only see 64 Ki B at once, but has 1 MiB of flash and 128 KiB of RAM. It bridges that gap with a 4-slot paging scheme and a system-call (“bcall”) mechanism that lets code on one 16 KiB flash page call routines on any other page. The OS is a single-tasking monitor: a boot/kernel core on flash page 0 (always mapped low), a large body of OS routines spread across the other flash pages and reached via bcalls, and a fixed RAM region holding the system state (flags, floating-point registers, display buffers, the variable table).